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Preliminary Technical Data
Table 41. Interrupt Enable Register 3 SFR (MIRQENH, 0xDB)
ADE7566/ADE7569
Bit No.
7 to 6
5
4
3
2
1
0
Interrupt Enable Bit
–
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Reserved
When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
7
6
5
GAIN[7:0]
4 3 2
1
0
The ADE7566/ADE7569 has two fully differential voltage input
0
0
0
0
0
0
0
0
channels. The maximum differential input voltage for input pairs
V P /V N and I P /I N is ±0.5 V. In addition, the maximum signal level
on analog inputs for V P /V N and I P /I N is ± 0.5 V with respect to
AGND.
Each analog input channel has a programmable gain amplifier
V P 1
GAIN (K)
SELECTION
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register in the
V IN
K × V IN
Energy Measurement Register List (see Table 35 and Figure 31).
Bit 0 to Bit 2 select the gain for the PGA in the current channel,
and Bit 5 to Bit 7 select the gain for the PGA in the voltage
channel. Figure 30 shows how a gain selection for the current
V N 1
Figure 30. PGA in Current Channel
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
channel is made using the gain register.
In addition to the PGA, Channel 1 also has a full-scale input
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
ADDR:
0x1B
range selection for the ADC. The gain register also selects the
ADC analog input range (see Figure 31). As mentioned
previously, the maximum differential input voltage is 0.5 V.
PGA 2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
CFSIGN_OPT
RESERVED
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
Figure 31. Analog Gain Register
Rev. PrA | Page 41 of 136
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